Edexcel GCSE Computer Science · 1CP2
Specification 3.1.1 · Paper 1
Revise: Von Neumann Architecture and the Fetch-Decode-Execute CycleFor a memory read, the address bus identifies where, the control bus communicates what operation to perform, and the data bus carries the contents. For a memory write, the CPU supplies the destination address, sends a write signal and transfers the data to memory.